
`define USE_YOSYS
`ifdef USE_YOSYS
(* blackbox *)
module cycloneive_clkctrl(
    ena,
	inclk,
	clkselect,
	devclrn,
	devpor,
	outclk
    );
	input wire ena;
	input wire[3:0] inclk;
	input wire[1:0] clkselect;
	input wire devclrn;
	input wire devpor;
	output wire outclk;
endmodule

module def_clk (
    clk_in,
    clk_out
);
    input wire clk_in;
    output wire clk_out;



    wire devclrn;
    wire devpor;
    wire devoe;
    wire outclk;
    // Location: CLKCTRL_G2
cycloneive_clkctrl inputclkctrl (
	.ena(1'b1),
	.inclk({1'b1,1'b1,1'b1,clk_in }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(outclk ));
// synopsys translate_off
defparam inputclkctrl .clock_type = "global clock";
defparam inputclkctrl .ena_register_mode = "none";
// synopsys translate_on


    assign clk_out = outclk;
endmodule

`else
module def_clk (
    clk_in,
    clk_out
);
    input wire clk_in;
    output wire clk_out;
    assign clk_out = clk_in;
endmodule
`endif


/*定义rv32黑盒*/
(* blackbox *)
module alta_rv32 (
  input         sys_clk,
  output        mem_ahb_hready,
  input         mem_ahb_hreadyout,
  output [1:0]  mem_ahb_htrans,
  output [2:0]  mem_ahb_hsize,
  output [2:0]  mem_ahb_hburst,
  output        mem_ahb_hwrite,
  output [31:0] mem_ahb_haddr,
  output [31:0] mem_ahb_hwdata,
  input         mem_ahb_hresp,
  input  [31:0] mem_ahb_hrdata,
  input         slave_ahb_hsel,
  input         slave_ahb_hready,
  output        slave_ahb_hreadyout,
  input  [1:0]  slave_ahb_htrans,
  input  [2:0]  slave_ahb_hsize,
  input  [2:0]  slave_ahb_hburst,
  input         slave_ahb_hwrite,
  input  [31:0] slave_ahb_haddr,
  input  [31:0] slave_ahb_hwdata,
  output        slave_ahb_hresp,
  output [31:0] slave_ahb_hrdata,
  input  [7:0]  gpio0_io_in,
  output [7:0]  gpio0_io_out_data,
  output [7:0]  gpio0_io_out_en,
  input  [7:0]  gpio1_io_in,
  output [7:0]  gpio1_io_out_data,
  output [7:0]  gpio1_io_out_en,
  output [1:0]  sys_ctrl_clkSource,
  output        sys_ctrl_hseEnable,
  output        sys_ctrl_hseBypass,
  output        sys_ctrl_pllEnable,
  input         sys_ctrl_pllReady,
  output        sys_ctrl_sleep,
  output        sys_ctrl_stop,
  output        sys_ctrl_standby,
  input  [7:0]  gpio2_io_in,
  output [7:0]  gpio2_io_out_data,
  output [7:0]  gpio2_io_out_en,
  input  [7:0]  gpio3_io_in,
  output [7:0]  gpio3_io_out_data,
  output [7:0]  gpio3_io_out_en,
  input  [7:0]  gpio4_io_in,
  output [7:0]  gpio4_io_out_data,
  output [7:0]  gpio4_io_out_en,
  input  [7:0]  gpio5_io_in,
  output [7:0]  gpio5_io_out_data,
  output [7:0]  gpio5_io_out_en,
  input  [7:0]  gpio6_io_in,
  output [7:0]  gpio6_io_out_data,
  output [7:0]  gpio6_io_out_en,
  input  [7:0]  gpio7_io_in,
  output [7:0]  gpio7_io_out_data,
  output [7:0]  gpio7_io_out_en,
  input  [7:0]  gpio8_io_in,
  output [7:0]  gpio8_io_out_data,
  output [7:0]  gpio8_io_out_en,
  input  [7:0]  gpio9_io_in,
  output [7:0]  gpio9_io_out_data,
  output [7:0]  gpio9_io_out_en,
  input         ext_resetn,
  output        resetn_out,
  output        dmactive,
  output        swj_JTAGNSW,
  output [3:0]  swj_JTAGSTATE,
  output [3:0]  swj_JTAGIR,
  input  [7:0]  ext_int,
  input  [3:0]  ext_dma_DMACBREQ,
  input  [3:0]  ext_dma_DMACLBREQ,
  input  [3:0]  ext_dma_DMACSREQ,
  input  [3:0]  ext_dma_DMACLSREQ,
  output [3:0]  ext_dma_DMACCLR,
  output [3:0]  ext_dma_DMACTC,
  input  [3:0]  local_int,
  input  [1:0]  test_mode,
  input         usb0_xcvr_clk,
  input         usb0_id
);

endmodule

(* blackbox *) (* keep *)
module alta_pllve
#(parameter N=3)
(
  input  clkin, clkfb,
  input  pfden, resetn,
  input  [2:0] phasecounterselect,
  input  phaseupdown, phasestep,
  input  scanclk, scanclkena, scandata, configupdate,
  output scandataout, scandone, phasedone,
  output clkout0, clkout1, clkout2, clkout3, clkout4,
  output clkfbout, lock
);
parameter coord_x         = 0;
parameter coord_y         = 0;
parameter coord_z         = 0;
parameter CLKIN_FREQ      = "20.0";
parameter CLKIN_HIGH      = 8'b0;
parameter CLKIN_LOW       = 8'b0;
parameter CLKIN_BYPASS    = 1'b0;
parameter CLKIN_TRIM      = 1'b0;
parameter CLKFB_HIGH      = 8'd36;
parameter CLKFB_LOW       = 8'd36;
parameter CLKFB_BYPASS    = 1'b0;
parameter CLKFB_TRIM      = 1'b0;
parameter CLKDIV0_EN      = 1'b0;
parameter CLKDIV1_EN      = 1'b0;
parameter CLKDIV2_EN      = 1'b0;
parameter CLKDIV3_EN      = 1'b0;
parameter CLKDIV4_EN      = 1'b0;
parameter CLKOUT0_HIGH    = 8'b0;
parameter CLKOUT0_LOW     = 8'b0;
parameter CLKOUT0_TRIM    = 1'b0;
parameter CLKOUT0_BYPASS  = 1'b0;
parameter CLKOUT1_HIGH    = 8'b0;
parameter CLKOUT1_LOW     = 8'b0;
parameter CLKOUT1_TRIM    = 1'b0;
parameter CLKOUT1_BYPASS  = 1'b0;
parameter CLKOUT2_HIGH    = 8'b0;
parameter CLKOUT2_LOW     = 8'b0;
parameter CLKOUT2_TRIM    = 1'b0;
parameter CLKOUT2_BYPASS  = 1'b0;
parameter CLKOUT3_HIGH    = 8'b0;
parameter CLKOUT3_LOW     = 8'b0;
parameter CLKOUT3_TRIM    = 1'b0;
parameter CLKOUT3_BYPASS  = 1'b0;
parameter CLKOUT4_HIGH    = 8'b0;
parameter CLKOUT4_LOW     = 8'b0;
parameter CLKOUT4_TRIM    = 1'b0;
parameter CLKOUT4_BYPASS  = 1'b0;
parameter CLKOUT0_DEL     = 8'b0;
parameter CLKOUT1_DEL     = 8'b0;
parameter CLKOUT2_DEL     = 8'b0;
parameter CLKOUT3_DEL     = 8'b0;
parameter CLKOUT4_DEL     = 8'b0;
parameter CLKOUT0_PHASE   = 3'b0;
parameter CLKOUT1_PHASE   = 3'b0;
parameter CLKOUT2_PHASE   = 3'b0;
parameter CLKOUT3_PHASE   = 3'b0;
parameter CLKOUT4_PHASE   = 3'b0;
parameter CLKFB_DEL       = 8'b0;
parameter CLKFB_PHASE     = 3'b0;
parameter FEEDBACK_MODE   = 3'b0;
parameter FBDELAY_VAL     = 3'b0;
parameter PLLOUTP_EN      = 1'b0;
parameter PLLOUTN_EN      = 1'b0;
parameter CLKOUT1_CASCADE = 1'b0;
parameter CLKOUT2_CASCADE = 1'b0;
parameter CLKOUT3_CASCADE = 1'b0;
parameter CLKOUT4_CASCADE = 1'b0;
parameter VCO_POST_DIV    = 1'b0;
parameter REG_CTRL        = 2'b0;
parameter IVCO            = 3'b100;
parameter CP              = 3'b010;
parameter RREF            = 2'b01;
parameter RLPF            = 2'b01;
parameter RVI             = 2'b01;
parameter PLL_EN_FLAG     = 1'b0;
endmodule

(* blackbox *) (* keep *)
module alta_gclksw (
  input  resetn, ena, clkin0, clkin1, clkin2, clkin3,
  input  [1:0] select,
  output clkout
);
parameter coord_x = 0;
parameter coord_y = 0;
parameter coord_z = 0;
parameter ENA_REG_MODE = 1'b0;
endmodule

(* blackbox *) (* keep *)
module alta_rio (
  input  datain, oe, outclk, outclkena, inclk, inclkena, areset, sreset,
  output combout, regout,
  inout  padio
);
endmodule

(* blackbox *)
module alta_gclkgen (
  input  clkin, ena, mode,
  output clkout
);
endmodule

(* blackbox *)
module alta_io_gclk (
  input inclk,
  output outclk
);
endmodule


module pll (
    ledout,
    gpio_pin,
    PIN_HSE,        //RC时钟
    PIN_HSI,        //晶振时钟
);
    output wire[3:0]     ledout;
    output wire[3:0]     gpio_pin;
    input PIN_HSE;
    input PIN_HSI;


    wire[7:0] gpio4_io_out_en;
    wire[7:0] gpio_pin_out;
    assign ledout[3:1] = gpio4_io_out_en[3:1];
    assign ledout[0] = PLL_CLKOUT[0];
    assign gpio_pin[0] = PLL_CLKOUT[1];
    assign gpio_pin[2] = sys_gck;
    assign gpio_pin[1] = mem_ahb_hwdata[0];


    //////////////////////////////////////////////////////////////////
    //调用PLL模块
    wire PLL_EN;
    wire PLL_LOCK;
    wire [4:0] PLL_CLKOUT;
    wire pll_clkfb;
    wire PIN_HSE_in;
    assign PIN_HSE_in = PIN_HSE;
    wire PIN_HSI_in;
    assign PIN_HSI_in = PIN_HSI;

defparam pll_inst.CLKIN_FREQ      = "8.0";
defparam pll_inst.CLKIN_HIGH      = 8'd0;
defparam pll_inst.CLKIN_LOW       = 8'd0;
defparam pll_inst.CLKIN_TRIM      = 1'b0;
defparam pll_inst.CLKIN_BYPASS    = 1'b0;
defparam pll_inst.CLKFB_HIGH      = 8'd36;
defparam pll_inst.CLKFB_LOW       = 8'd37;
defparam pll_inst.CLKFB_TRIM      = 1'b1;
defparam pll_inst.CLKFB_BYPASS    = 1'b0;
defparam pll_inst.CLKDIV0_EN      = 1'b1;
defparam pll_inst.CLKDIV1_EN      = 1'b1;
defparam pll_inst.CLKDIV2_EN      = 1'b1;
defparam pll_inst.CLKDIV3_EN      = 1'b0;
defparam pll_inst.CLKDIV4_EN      = 1'b0;
defparam pll_inst.CLKDIV4_EN      = 1'b0;
defparam pll_inst.CLKOUT0_HIGH    = 8'd0;
defparam pll_inst.CLKOUT0_LOW     = 8'd1;
defparam pll_inst.CLKOUT0_TRIM    = 1'b1;
defparam pll_inst.CLKOUT0_BYPASS  = 1'b0;
defparam pll_inst.CLKOUT0_DEL     = 8'd0;
defparam pll_inst.CLKOUT0_PHASE   = 3'd0;
defparam pll_inst.CLKOUT1_HIGH    = 8'd0;
defparam pll_inst.CLKOUT1_LOW     = 8'd4;
defparam pll_inst.CLKOUT1_TRIM    = 1'b1;
defparam pll_inst.CLKOUT1_BYPASS  = 1'b0;
defparam pll_inst.CLKOUT1_DEL     = 8'd0;
defparam pll_inst.CLKOUT1_PHASE   = 3'd0;
defparam pll_inst.CLKOUT2_HIGH    = 8'd255;
defparam pll_inst.CLKOUT2_LOW     = 8'd255;
defparam pll_inst.CLKOUT2_TRIM    = 1'b0;
defparam pll_inst.CLKOUT2_BYPASS  = 1'b0;
defparam pll_inst.CLKOUT2_DEL     = 8'd0;
defparam pll_inst.CLKOUT2_PHASE   = 3'd0;
defparam pll_inst.CLKOUT3_HIGH    = 8'd255;
defparam pll_inst.CLKOUT3_LOW     = 8'd255;
defparam pll_inst.CLKOUT3_TRIM    = 1'b0;
defparam pll_inst.CLKOUT3_BYPASS  = 1'b0;
defparam pll_inst.CLKOUT3_DEL     = 8'd0;
defparam pll_inst.CLKOUT3_PHASE   = 3'd0;
defparam pll_inst.CLKOUT4_HIGH    = 8'd255;
defparam pll_inst.CLKOUT4_LOW     = 8'd255;
defparam pll_inst.CLKOUT4_TRIM    = 1'b0;
defparam pll_inst.CLKOUT4_BYPASS  = 1'b0;
defparam pll_inst.CLKOUT4_DEL     = 8'd0;
defparam pll_inst.CLKOUT4_PHASE   = 3'd0;
defparam pll_inst.FEEDBACK_MODE   = 3'b100;
defparam pll_inst.FBDELAY_VAL     = 3'b100;
defparam pll_inst.VCO_POST_DIV    = 1'b1;
(* keep *) alta_pllve
 pll_inst (
  .clkin(PIN_HSE_in),
  .pfden(1'b1),
  .resetn(PLL_EN),
  .phasecounterselect(3'b0),
  .phaseupdown(1'b0),
  .phasestep(1'b0),
  .scanclk(1'b0),
  .scanclkena(1'b0),
  .scandata(1'b0),
  .configupdate(1'b0),
  .clkfb(pll_clkfb),
  .clkfbout(pll_clkfb),
  .clkout0(PLL_CLKOUT[0]),
  .clkout1(PLL_CLKOUT[1]),
  .clkout2(PLL_CLKOUT[2]),
  .clkout3(PLL_CLKOUT[3]),
  .clkout4(PLL_CLKOUT[4]),
  .lock   (PLL_LOCK));

    wire sys_resetn;
    wire[1:0] sys_ctrl_clkSource;
    wire sys_ctrl_stop;
    wire sys_clk;

    alta_gclksw gclksw_inst (
    .resetn(sys_resetn),
    .ena   (!sys_ctrl_stop),
    .clkin0(PIN_HSI_in),
    .clkin1(PIN_HSE_in),
    .clkin2(PLL_CLKOUT[1]),
    .clkin3(),
    .select(sys_ctrl_clkSource),
    .clkout(sys_clk));

/////////////////////////
//不知道为什么需要添加下面这两个模块.否则supra综合时会停止运行
    wire sys_gck;
    assign bus_clk = sys_gck;

(* keep *) alta_gclkgen gclksw_gen (
    .clkin (sys_clk),
    .ena   (!sys_ctrl_stop),
    .clkout(sys_gck0));

// Location: CLKCTRL_G5 FIXED_COORD
(* keep *) alta_io_gclk gclksw_gclk (
    .inclk (sys_gck0),
    .outclk(sys_gck));


//////////////////////////////////////////////////////////////////

  wire[31:0] mem_ahb_haddr;
  wire[31:0] mem_ahb_hwdata;

    alta_rv32 rv32(
		    .sys_clk(sys_clk),
        .gpio4_io_in(8'b01010101),
        .gpio4_io_out_en(gpio4_io_out_en),

        .sys_ctrl_pllEnable(PLL_EN),
        .sys_ctrl_pllReady(PLL_LOCK),

        .sys_ctrl_clkSource(sys_ctrl_clkSource),
        .sys_ctrl_stop(sys_ctrl_stop),
        .resetn_out(sys_resetn),



        .gpio4_io_out_data(gpio_pin_out),

		    .ext_int(8'b0),
        .local_int(4'b0),
			  .test_mode(2'b0),

		    .mem_ahb_haddr(mem_ahb_haddr),
        .mem_ahb_hwdata(mem_ahb_hwdata),
		    .mem_ahb_hreadyout(1'b1)

		  // .slave_ahb_hready(1'b1),

			// .mem_ahb_hresp(1'b0),
			// .mem_ahb_hrdata(32'h0),
			// .slave_ahb_hsel(1'b0),
			// .slave_ahb_htrans(2'b0),
			// .slave_ahb_hsize(3'b0),
			// .slave_ahb_hburst(3'b0),
			// .slave_ahb_hwrite(1'b0),
			// .slave_ahb_haddr(32'b0),
			// .slave_ahb_hwdata(32'b0),
			// .ext_resetn(1'b0),

			// .ext_dma_DMACBREQ(4'b0),
			// .ext_dma_DMACLBREQ(4'b0),
			// .ext_dma_DMACSREQ(4'b0),
			// .ext_dma_DMACLSREQ(4'b0),

			// .usb0_xcvr_clk(1'b0),
			// .usb0_id(1'b0)

    );


endmodule